1. Field of the Invention
The present invention relates to a semiconductor device comprising a shallower trench and a deeper trench in one semiconductor substrate, and more particularly relates to a method for manufacturing a semiconductor device, which enables to form a shallow trench with higher depth dimension accuracy.
2. Related Art
In semiconductor devices such as memory and the like, a cell region and a peripheral region are typically disposed on one semiconductor substrate, and these regions are driven at different voltages. In such semiconductor device, a device isolation insulating film for isolating devices formed in each of the regions is required to be designed corresponding to the driving voltages. More specifically, in the peripheral region utilizing higher driving voltage, the film thickness of the device isolation insulating film is thicker in order to ensure maintaining sufficient breakdown voltage resistance for device isolation, and in the cell region utilizing lower driving voltage, the film thickness of the device isolation insulating film is thinner in order to achieve a miniaturization of the device rather than ensuring sufficient breakdown voltage resistance for device isolation. Particularly in recent years, shallow trench isolation (STI) insulating film provided by forming a trench on the semiconductor substrate and filling thereof with an insulating film is proposed, and when the STI is employed for the device isolation, STI having relatively deeper trench is formed in the peripheral region and STI having relatively shallower trench is formed in the cell region.
As such, it is required to form respective trenches having respective depths, in order to form semiconductor devices including STI having different depths on one semiconductor substrate. A technology for forming trenches having such different depths is disclosed in Japanese Patent Laid-Open No. 2001-168184. This technology will be described in reference to FIGS. 8A to 8D. As shown in FIG. 8A, a silicon oxide film 231 and a silicon nitride film 232 are consecutively formed on a silicon substrate 201; a part of the silicon nitride film 232 around a peripheral region 260 for forming deeper STI is etched through a first photo resist pattern 233 to form openings; the silicon oxide film 231 is etched through the silicon nitride film 232 as a mask, and further, the silicon substrate 201 is etched to a predetermined depth to form trenches 211Ba. Then, as shown in FIG. 8B, a second photo resist pattern 234 is formed, where the widths of the openings thereof are wider than that of the first photo resist pattern 233 to reduce the line width dimension in the peripheral region 260 for forming deeper STI. Then, the silicon nitride film 232 is etched through the second photo resist pattern 234. Then, as shown in FIG. 8C, the silicon oxide film 231 is etched through the mask of the silicon nitride film 232, and further the silicon substrate 201 is etched. Thereafter, as shown in FIG. 8D, the silicon oxide film 231 and the silicon nitride film 232 are removed to form trenches 211A and 211B having different depths in one silicon substrate 201. In this case, as shown in FIG. 8C, since the trenches 211Ba, which have been etched, are further etched to form a deeper depth in the peripheral region 260 having the deeper STI formed thereon, the trenches 211B are formed to have a deeper depth than the trenches 211A formed via an etching in the cell region 250 for forming shallow STI.
In the technology described in Japanese Patent Laid-Open No. 2001-168184, when the second photo resist pattern 234 is formed, it is necessary to conduct an alignment of the pattern of the silicon nitride film 232 formed through the first photo resist pattern 233 with higher accuracy. It is necessary to align the second photo resist pattern 234 with higher accuracy, particularly in the case of semiconductor devices that require further miniaturization, and thus a problem of unwantedly providing a complicated process for manufacturing the second photo resist pattern 234 is arisen.
On the other hand, Japanese Patent Laid-Open No. 1985-92632 discloses a technology, in which the required accuracy for aligning the second photo resist pattern process can be reduced. In this technology, firstly as shown in FIG. 9A, a phosphor silicate glass (PSG) film 331 and a silicon oxide film 332 are formed consecutively on a surface of a silicon substrate 301. A first photo resist pattern 333 is formed, and the silicon oxide film 332 in regions for forming STI is partially etched through the first photo resist pattern. Next, as shown in FIG. 9B, the second photo resist pattern 334 is formed to cover the cell region 250, and then the PSG film 331 in the peripheral region 260 is partially etched. In this occasion, since the silicon substrate 301 is also slightly etched, trenches 311Ba having a predetermined depth are simultaneously formed. Subsequently, as shown in FIG. 9C, the second photo resist pattern 334 is removed, and thereafter, the remaining portions of the PSG film 331 are etched through a mask of the silicon oxide film 332, and the silicon substrate 301 is additionally etched to further etch the trenches 311Ba that have been previously formed in the peripheral region 260, thereby forming deeper trenches 311B. In addition, trenches 311A are also formed in the cell region 250, and in this case, since the PSG film 331 should be etched off before etching the silicon substrate in an early stage of the etch process, the etch depth of the silicon substrate 301 is slightly reduced as a trade-off of the etching of the PSG film, and therefore the trenches 311A are formed as relatively shallower trenches. Thereafter, as shown in FIG. 9D, the silicon oxide film 332 and the PSG film 331 are removed to form trenches 311A and 311B having different depths on one silicon substrate 301. Since the function of the second photo resist pattern 334 is to only cover the cell region in the technology disclosed in Japanese Patent Laid-Open No. 1985-92632, the required accuracy for aligning thereof may be lower in comparison with the technology disclosed in Japanese Patent Laid-Open No. 2001-168184, and thus a simple masking process can be utilized.
Another type of technology is also proposed, in which the PSG film and the silicon oxide film utilized in the technology of Japanese Patent Laid-Open No. 1985-92632 are replaced with the silicon oxide film and the silicon nitride film, respectively, similarly as in Japanese Patent Laid-Open No. 2001-168184. Since this technology is substantially similar to the technology of Japanese Patent Laid-Open No. 1985-92632, the illustration in reference to figures is not presented here. The process is as follows. Silicon nitride films in a peripheral region and a cell region for forming STI are partially etched through a mask of a first photo resist pattern, and thereafter, the cell region is coated through a mask of a second photo resist pattern, and then only portions of a silicon oxide film in the peripheral region are removed to partially expose the silicon substrate. Then, an etch process is conducted for the peripheral region and the cell region, where only the silicon substrate is etched in the peripheral region and the silicon oxide film and the silicon substrate are etched in the cell region. The trenches in the cell region are shallower than the trenches in the peripheral region, since the etch amount in etching the silicon substrate is reduced by an amount of etching the silicon oxide film in the cell region. The required accuracy for aligning the second photo resist in the masking process can also be reduced even in this technology.